Google’s Top 10 Celebrity Searches of 2018 Revealed | 2018 Year in Review – Just Jared

Google’s Top 10 Celebrity Searches of 2018 Revealed | 2018 Year in Review – Just Jared

Google has just revealed their data for the top 10 famous figures searched on their site throughout 2018.

The top 10 names are all celebrities, entertainers, reality stars, public figures, or in the sports world. All the data collected is related to searches within the United States only.

If you’re looking for some other year-end coverage, you can check out more such as finding out the top 10 most binge watched shows on Netflix in 2018!

Click through the slideshow to see the top 10 people searched for on Google in 2018…

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Intel’s Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86 – AnandTech

Intel’s Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86 – AnandTech

It has been hard to miss the fact that Intel has been vacuuming up a lot of industry talent, which brings with them a lot of experience. Renduchintala, Koduri, Keller, Hook, and Carvill, are just to name a few. This new crew has decided to break Intel out of its shell for the first time in a while, holding the first in a new tradition of Intel Architecture Days. Through the five hours of presentations, Intel lifted the lid on the CPU core roadmaps through 2021, the next generation of integrated graphics, the future of Intel’s graphics business, new chips built on 3D packaging technologies, and even parts of the microarchitecture for the 2019 consumer processors. In other words, it’s many of the things we’ve been missing out on for years. And now that Intel is once again holding these kinds of disclosures, there’s a lot to dig in to.

Contents List

Intel covered a good amount of ground at the Architecture Day, which we’ve split into the following categories:

  1. The CPU Core and Atom Roadmaps, on 10nm
  2. The Sunny Cove Microarchitecture
  3. The Next Generation Gen11 Graphics
  4. Intel Demonstrates Sunny Cove and Gen11 Graphics
  5. Beyond Gen11 Graphics: Announcing the Xe Graphics Brand
  6. 3D Packaging with FOVEROS
  7. Intel’s first Fovoros and first Hybrid x86 CPU: Core plus Atom in 7 W on 10nm
  8. Ice Lake 10nm Xeon
  9. Intel Made Something Really Funny: Q&A with Raja, Jim, and Murthy

 

The CPU Core Roadmaps

It is common for companies like Intel to ask members of the press what they enjoy about announcements from Intel, Intel’s competitors, or other companies in the industry. One of answers I will never tire of saying is ‘roadmaps’. The roadmap is a simple document but it enables a company to explain part of its future plans in a very easy to understand way. It shows to the press, to customers, and to partners, that the company has a vision beyond the next product and that it expects to deliver at a rough cadence, hopefully with some markers on expected performance additions or improvements. Roadmaps are rarely taken as set in stone either, with most people understanding that they have an element of fuzziness depending on external factors.

To that end, I’ve been requesting Intel to show roadmaps for years. They used to be common place, but ever since Skylake, it has kind of dried up. In recent months Intel has shown rough datacentre roadmaps, with Cascade Lake, Cooper Lake, and Ice Lake and the next few generations. But for the Core family it has been somewhat more difficult. Depending on which analyst you talk to, a good number will point to some of the Skylake derivatives as being holding points while the issues with 10nm have been sorted out. But nonetheless, all we tend to hear about is the faint whisper of a codename potentially, which doesn’t mean much.

So imagine my delight when we get not one roadmap from Intel on CPUs, but two. Intel gave us both the Core architecture roadmap and the Atom architecture roadmap for the next few generations.

For the high performance Core architecture, Intel lists three new codenames over the next three years. To be very clear here, these are the codenames for the individual core microarchitecture, not the chip, which is an important departure from how Intel has previously done things.

Sunny Cove, built on 10nm, will come to market in 2019 and offer increased single-threaded performance, new instructions, and ‘improved scalability’. Intel went into more detail about the Sunny Cove microarchitecture, which is in the next part of this article. To avoid doubt, Sunny Cove will have AVX-512. We believe that these cores, when paired with Gen11 graphics, will be called Ice Lake.

Willow Cove looks like it will be a 2020 core design, most likely also on 10nm. Intel lists the highlights here as a cache redesign (which might mean L1/L2 adjustments), new transistor optimizations (manufacturing based), and additional security features, likely referring to further enhancements from new classes of side-channel attacks.

Golden Cove rounds out the trio, and is firmly in that 2021 segment in the graph. Process node here is a question mark, but we’re likely to see it on 10nm and or 7nm. Golden Cove is where Intel adds another slice of the serious pie onto its plate, with an increase in single threaded performance, a focus on AI performance, and potential networking and AI additions to the core design. Security features also look like they get a boost.

Intel Core Microarchitecture Roadmap
Core Name Year Process Node Improvements
Skylake 2015 14 nm Single Threaded Performance
Lower Power
Other Optimizations
Kaby Lake 2016 14 nm+ Frequency
Coffee Lake 2017 14 nm++ Frequency
Coffee Refresh 2018 14 nm++ Frequency
Sunny Cove 2019 10 nm Single Threaded Performance
New Instructions
Improved Scalability
Willow Cove 2020 ? 10 nm ? Cache Redesign
New Transistor Optimization
Security Features
Golden Cove 2021 ? 7 / 10 nm ? Single Threaded Performance
AI Performance
Networking / 5G Performance
Security Features

The lower-powered Atom microarchitecture roadmap is on a slower cadence than the Core microarchitecture, which is not surprising given its history. Seeing as how Atom has to fit into a range of devices, we’re expecting there to be a wide range in capabilities, especially from the SoC side.

The upcoming microarchitecture for 2019 is called Tremont, which focuses on single threaded performance increases, battery life increases, and network server performance. Based on some of the designs later in this article, we think that this will be a 10nm design.

Following Tremont will be Gracemont, which Intel lists as a 2021 product. As Atom is designed to continually push both the performance at the high-end of its capabilities and the efficiency at the low-end, Intel lists that Gracemont will have additional single threaded performance and a focus on increased frequency. This will be combined with additional vector performance, which likely means that Atom will get some wider vector units or support new vector instructions.

Beyond this will be a future ‘mont’ core (and not month as listed in the image). Here Intel is spitballing what this new 2023 core might have, for which the general listing of performance, frequency and features is there.

Intel Atom Microarchitecture Roadmap
  Year Process Improvements
Goldmont 2016 14 nm Higher Performance
Cryptography Features
Goldmont Plus 2017 14 nm Branch Prediction
More Execution
Larger Load/Store Buffers
More Cache
2018
Tremont 2019 10 nm ? Single Threaded Performance
Network Server Performance
Battery Life
2020
Gracemont 2021 10 nm ? Single Threaded Performance
Frequency
Vector Performance
2022
‘Next Mont’ 2023 ? Single Threaded Performance
Frequency
‘Features’

As stated above, these are just the microarchitecture names. The actual chips these cores are in will likely have different names, which means a Lake name for the Core microarchitecture. At the event, Intel stated that Ice Lake would have Sunny Cove cores in it, for example.

Another aspect to Intel’s presentations was that future microarchitectures are likely to be uncoupled from any process technologies. In order to build some resiliency into the company’s product line moving forward, both Raja Koduri and Dr. Murthy Renduchintala explained that future microarchitectures will not be process dependent, and the latest products will come to market on the best process technologies available at the time. As a result we’re likely to see some of the Core designs straddle different manufacturing technologies.

Intel also went into a bit of detail on microarchitecture of Sunny Cove.

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Intel introduces Foveros: 3D die stacking for more than just memory – Ars Technica

Intel introduces Foveros: 3D die stacking for more than just memory – Ars Technica
P1274 is Intel's name for its high performance 10nm process. P1222 is its 22FFL (22nm, FinFET, Low Power) process, which is optimized for much lower current leakage. As well as the Foveros connection between the compute and I/O modules, the product will use conventional stacked Package-on-Package memory.
Enlarge
/ P1274 is Intel’s name for its high performance 10nm process. P1222 is its 22FFL (22nm, FinFET, Low Power) process, which is optimized for much lower current leakage. As well as the Foveros connection between the compute and I/O modules, the product will use conventional stacked Package-on-Package memory.

Intel

In 2019, Intel is going to ship chips using a new 3D stacking technology the company is calling Foveros. Foveros allows complex logic dies to be stacked upon one another, providing a much greater ability to mix and match processor components with optimal manufacturing processes.

Package-on-package stacking is already commonplace in the system-on-chip world. Typically, this involves sticking a memory package on top of a processor, with perhaps a few hundred connections between the two. The size and performance of the connections has limited the application of this technique. With Foveros, the interconnect will use etched silicon (just as EMIB does) to enable many more interconnections, running at much greater speeds.

Foveros follows on from Intel’s EMIB (Embedded Multi-die Interconnect Bridge) tech. EMIB is found on the Kaby Lake-G processors that in a single package contain an Intel CPU, AMD GPU, and a chunk of second-generation High Bandwidth Memory (HBM). HBM achieves its high bandwidth by using thousands of interconnects between the GPU and its memory, in comparison to the several hundred used between a GPU and conventional GDDR. The Kaby Lake-G chips use EMIB to provide this connection.

Instead of EMIB’s silicon bridges, Foveros uses thousands of “microbumps” on the chip faces, with direct face-to-face connections between the stacked parts. The interposer that the chips connect to isn’t just inert silicon with some traces, as in EMIB, but a chip in its own right, with its own logic built in.

Foveros' microbumps enable face-to-face communication between dies.
Enlarge
/ Foveros’ microbumps enable face-to-face communication between dies.

Intel

The high performance of Foveros means that core processor components can be distributed between different dies. For example, high performance CPU cores might be built on the highest performance 10nm process. But I/O connectivity—integrated USB, Wi-Fi, Ethernet, PCIe—doesn’t need all that performance, because it’s constrained by the limitations of the physical interfaces it must support. Accordingly, it might make more sense to use a low-power 14nm or even 22nm process for this portion of the chip. Performance will still be good enough, but at much lower power usage or cost than if it had to use the same high-performance process as the logic. Similarly, analog components (for Wi-Fi and cellular connectivity) are optimal on different processes, with different transistor designs. Foveros means that a processor can integrate such components, while still letting them use a process that’s optimized for that particular usage.

With EMIB, these different components could be tightly packaged together side by side. Foveros takes that into the third dimension, enabling even greater density and a reduced footprint. Intel anticipates that different CPU tasks will increasingly be split up into chiplets, then combined in a mix-and-match way for the finished chip. Low-power components such as I/O and power delivery will be put into a base die, with high-performance logic stacked on top.

Intel says that Foveros products will be shipping in the second half of 2019 and that the technology is ready for mass-market production—not just specialized or customized processors, but mainstream CPUs. The first products will combine 10nm compute logic stacked on top of a base die using the company’s 22FFL (FinFET Low power) process, topped off with package-on-package memory. The 10nm part will contain both a Sunny Cove high power core, and four Atom cores, in a style that is familiar from modern ARM processors: light workloads will be able to use the low power Atom cores, but the Sunny Cove can be powered up for more computationally expensive tasks. This chip will be aimed at ultra-mobile systems with the processor measuring 12×12×1mm and having a standby power of 2mW.

Intel’s not the only one to want to use different processes for different bits of a processor. AMD has already announced that its next-generation Zen 2 processors will be separating its CPU logic from I/O. The CPU logic will be on chiplets built on a 7nm process. But everything else—including PCIe, DDR, USB, SATA—will be on a separate 14nm I/O die. AMD will likely be using a conventional multichip module for Zen 2; the different parts will all be connected to a PCB that joins them all together.

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Fallout 76’s New Ultrawide Mode Comes Under Fire From Players – IGN

Fallout 76’s New Ultrawide Mode Comes Under Fire From Players – IGN


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Bethesda gets more flak from players with this week’s patch.

Bethesda has irked PC players with the new 21:9 resolution support in Fallout 76’s latest patch.

This week’s Fallout 76 patch saw a number of changes roll out for the game, including adding ultrawide screen resolution support. However, players on Reddit have discovered that the new ultrawide mode appears to be nothing more than a modification to the INI file, meaning that 16:9 aspect ratio has been stretched to meet the wider resolution, rather than being a true 21:9 display.

The result is that, while the game appears to render correctly in 21:9, the UI doesn’t adjust accordingly, stretching unnaturally.

Redditor AbheekG took screenshots of the game’s ultrawide mode comparing it to unoffical ultrawide mods for both Fallout 4 and Fallout 76, commenting that, “A modder without access to the source code did what Bethesda didn’t in a whole month!”

A number of other commentors in the thread have experienced the same result after the patch.

The unofficial workaround to get the game to support ultrawide resolutions by simply editing a line of code in the INI files has been around since launch, so players aren’t too happy that the official 21:9 resolution support is nothing more than a stretched version of the 16:9 display.

Patch 1.0.3.10 also added a number of fixes, including a bug in the Feed the People event quest, which has seen players asking the developer to roll back the fix. The bugged version resulted in a server-wide reward of Canned Meat Stew regardless of player participation in the event. Since the update, players have taken to Reddit asking Bethesda to “unfix the Feed The People event.”

Bethesda has said it may drop one more patch before the end of the year, before it shifts its focus to 2019 updates, which will include new content for the game, as well as “many additional bug fixes, and more changes” based on player feedback.

Shabana is a freelance writer who enjoys JRPGs, wine, and not finishing games. Follow her on Twitter and Instagram.

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